Providing clocks of accurate and well-defined phases is one of the essential requirements for correct operation of various kinds of sequential circuits. For instance, an interface circuit handling signal input/output is one of the most important sequential circuits of modern integrated circuits. As an example, consider a chip (die) which needs to receive an incoming serial signal; an interface circuit of the chip will include a clock data recovery (CDR) circuit for retrieving clock embedded in the serial signal and accordingly sampling the serial signal to obtain bit data serially arranged in the serial signal. Please refer to FIG. 1 illustrating a CDR operated by half-rate sampling.
As shown in FIG. 1, for latching a serial signal Din, half-rate sampling utilizes four clocks CK0, CK90, CK180 and CK270 of equal frequency (period) and quadrature phases (phase different by a quarter of a period). The serial signal Din includes a plurality of serially arranged unit data (e.g., bit data), such as the unit data D1 and D2; each unit data lasts for a duration UI. The period T of the four clocks CK0 to CK270 is double of the duration UI, i.e., T=2*UI. Therefore, if edges (e.g., rising edges) of the clocks CK90 and CK270 are tuned to align transitions between the serially arranged unit data, then edges (e.g., rising edges) of the clocks CK0 and CK180 will locate at centers of the unit data for optimal sampling of digital contents of each unit data.
By illustration of FIG. 1, providing high quality clocks of accurate quadrature phases is one of the essential keys for correct half-rate sampling; the phase differences between the clocks CK0, CK90, CK180 and CK270 should closely approach or equal 90 degrees to achieve successful CDR. If the mutual phase differences between the clocks CK0, CK90, CK180 and CK270 deviate from ideal 90 degrees, correctness of CDR is jeopardized.
Please refer to FIG. 2 illustrating a prior art clock generation for providing clocks PI0, PQ0, PI180 and PQ180 as the clocks CK0, CK90, CK180 and CK270 shown in FIG. 1. The prior art shown in FIG. 2 utilizes two phase interpolators 10a and 10b, each phase interpolator has four clock input terminals in0, in90, in180 and in270, as well as a weighting input terminal code_in; each phase interpolator receives a variable weighting a0 from the weighting input terminal code_in, and performs phase interpolation between clocks received from the clock input terminals in0 to in270 based on the weighting a0 to generate two output clocks of opposite phases. The phase interpolator 10a has its input terminals in0, in90, in180 and in270 respectively coupled to four input clocks S0, S90, S180 and S270 to generate two output clocks PI0 and PI180 of opposite phases (a phase difference of 180 degrees), such that phase of the clock PI0 can be expressed by (a0*PH+(1-a0)*PH90); wherein phases PH0 and PH90 are the respective phases of the clocks S0 and S90, and the weighting a0 is between 0 and 1. On the other hand, the phase interpolator 10b has its input terminals in0, in90, in180 and in270 respectively coupled to the input clocks S270, S0, S90 and S180 to generate two output clocks PQ0 and PQ180 of opposite phases, and a phase of the clock PQ0 can be expressed by (a0*PH90+(1-a0)*PH180); where phase PH180 is phase of the clock S180.
For the prior art shown in FIG. 2, an ideal phase difference (PH90−PH0) between the clocks S0 and S90 is 90 degrees, and an ideal phase difference (PH180−PH90) between the clocks S90 and S180 is also 90 degrees; under such ideal scenario, a phase difference between the clocks PI0 and PQ0 can be calculated as: {a0*PH90+(1-a0)*PH180}−{a0*PH0+(1-a0)*PH90}=a0*(PH90−PH))+(1-a0)*(PH180−PH90)=90. That is, if the phase differences between the input clocks S0, S90 and S180 equal 90 degrees, the phase difference between the clocks PI0 and PQ0 will also be kept at 90 degrees; by tuning value of the weighting a0 to align the clocks PI0 and PQ0 with transitions between unit data of a serial signal, CDR can be accomplished by the clocks PI0, PQ0, PI180 and PQ180.
However, because the clocks S0 to S270 are transmitted to phase interpolators by clock tree, many non-ideal factors (e.g., noise and mismatch between clock transmission paths and related elements, etc.) affect phase differences between the clocks S0 to S270; although the clocks S0 and S180 can be kept at 180-degree opposite phases by cross-couple pairing, the phase difference (PH90−PH0) between the clocks S0 and S90 deviates from ideal 90 degrees to be expressed by (PH90−PH0)=(90+PHoff); wherein PHoff is a phase offset. Consequently, the phase difference between the clocks S90 and S180 is expressed by (PH180−PH90)=(90−PHoff). After phase interpolation, the phase difference between the clocks PI0 and PQ0 therefore also deviates from 90 degrees; the deviation is proportional to the phase offset PHoff. Since the phase difference between the clocks PI0 and PQ0 violates ideal quadrature phase relation of 90 degrees, the prior art fails to correctly perform CDR.